Future intelligent power ICs will require high-density power devices along with analog functions and VLSI logic. DMOS transistors are important in power device applications capable of handling high voltages. For such devices, one figure of merit is the current handling capacity per unit area or the ON resistance per unit area. For a given voltage rating, the ON resistance per unit area may be reduced by reducing the cell area of the MOS device. In the field of power transistors, the combined width of the polycrystalline silicon (polysilicon) and the contact region, which forms the gate and source electrode, respectively, is defined as the cell pitch of the device. For a DMOS power transistor, a known technique to reduce the width of the polysilicon region is to decrease the P-well junction depth. However, minimum junction depth is defined by the breakdown voltage required.
A conventional lateral DMOS (LDMOS) device is typically well suited for incorporation into VLSI processes because of its simplicity. However, LDMOS devices have been considered inferior to vertical DMOS (VDMOS) devices, and therefore have not received significant attention. Recently, a RESURF (Reduced SURface Field) LDMOS device with good specific on-resistance (R.sub.sp) has been demonstrated. But that device structure is more complex and not very versatile because it is typically limited to grounded source applications. More specifically, in the past, DMOS transistors have been utilized either as discrete power transistors or as components in monolithic integrated circuits. DMOS transistors are inherently conservative of semiconductor substrate area because of the manner in which they are fabricated in a self-aligned fabrication sequence. A channel body region is usually formed first by introduction of one type of dopant (P or N impurities) through an aperture in a mask of gate-forming material. This provides a channel region which is self-aligned to the gate electrode. Then a source region is usually formed by dopant introduction of a type opposite to that of the channel body region through the existing aperture so that the source is self-aligned to both the gate electrode and the channel body region. This permits a very compact structure.
Referring now to FIGS. 1A and 1B, a conventional method for fabricating a typical DMOS transistor is described. First, as shown in FIG. 1A, a field oxide layer 2 is formed on a P-type semiconductor substrate 1 according to a well-known LOCOS (local oxidation of silicon) process in the art. Then, a layer 4 of oxide (silicon dioxide) is preferably thermally grown or deposited over the surface of the substrate 1 including over the substrate surface. This oxide layer 4 will preferably and subsequently serve as the gate insulator of the completed DMOS device. Next, 5000 .ANG. of polycrystalline silicon, for example, may be deposited on the insulating layer 4 and patterned, preferably by a conventional photolithographic masking and etching technique, to yield one or more conductive gate electrode regions 5 with each gate electrode region 5 serving as the gate electrode for a completed DMOS device. Also on the substrate, a photoresist layer is deposited and patterned to form a body forming mask 6. A P-type body region 8 is formed in the surface of the P-type substrate 1 by, for example, conventional photolithographic masking, etching and diffusion techniques using a P-type dopant source 7 such as boron.
Particularly, so as to render high conductivity to the gate electrode regions 5, a POCI.sub.3 doping or a ion implantation step has been used before performing a heat treatment step at high temperature. If desired, ion implantation techniques can be used to form the P-type body 8. The number of P-type bodies formed depends on whether a discrete DMOS device is being formed or whether one or more DMOS devices are being used as unit cells of an integrated circuit power device. The P-type body 8 doped with P-type dopants will eventually be used as the high conductivity (i.e., low resistivity) contact regions for the body channel of the completed DMOS device.
However, during fabrication of such a DMOS device using POCI.sub.3 doping and heat treatment (particularly for power devices), there arise at least two problems. One of the problems is that the channel region in the P-type body 8 has a nonuniform doping profile. This is because the P-type impurity injected into the gate electrode region 18 is diffused downwardly and laterally during the formation of the P-type body 8 and an N.sup.+ drain/source region therein. More particularly, a region of the P-type body which is nearly adjacent to the drain region has a rather low concentration of impurities therein. As a result, if an increased drain voltage is applied to the completed DMOS device, the drain region which is nearly adjacent to the channel region is easily depleted and susceptible to punchthrough. Accordingly, the electrical characteristics of the completed DMOS device, particularly the withstand voltage, can be seriously degraded.
In order to prevent the above described withstand voltage from being lowered, it is typically necessary to increase the channel length between the P-type body and the source region. This, however, increases the lateral dimensions of the DMOS device and reduces integration density. The other of the problems is that it is difficult to make the gate polysilicon have high conductivity by diffusing an N-type conductive source such as, POCI.sub.3, WSi.sub.X or the like. This is because the P-type body 8 is previously formed by doping with P-type impurities before diffusion of the conductive N-type source in the gate polysilicon. If the conductive gate is formed by diffusion of POCI.sub.3, an additional masking layer may be necessary to block P-type impurities during formation of the conductive gate. Also, when the conductive gate is formed without the use of such an additional masking layer, an impurity ion implantation step may need to be performed in place of the diffusion of POCI.sub.3. In the event an ion implantation step is performed, the resistance of the conductive gate may be undesirably increased. When diffusion of WSi.sub.X is used, an additional problem associated with lift-off may occur.
Moreover, if an ion implantation step for forming the P-type body is performed before forming a gate electrode region, there may arise a problem of misalignment during the formation of the P-type body. Such misalignment may degrade the electrical characteristics of the DMOS device. Additionally, it is typically necessary to form a very low-resistance channel between the channel body region and the source region to prevent undesired parasitic transistor action that may occur if the source/body P-N junction becomes forward biased at high current levels. Because the channel body region is lightly doped, and a low resistance electrical contact to a semiconductor region typically requires a heavily-doped surface region, it is necessary to provide an auxiliary heavily doped contact region for the channel body region to insure good electrical contact to both the source and body regions. Such a heavily doped body region usually cannot be self-aligned and hence there may be an increase in the overall size of the DMOS device. Typically, the heavily doped body contact region is formed before the other two regions. Then a rather thick masking oxide layer is used to protect the heavily doped body contact region against the source region dopant. The necessity to etch away or remove this masking oxide layer together with any oxide over the source regions, without disturbing the insulator over and/or under the gate electrode, increases fabrication costs, tolerances, and process complexity and, as a result, decreases the yields of electrically good devices.
While various processes having been utilized in an attempt to ameliorate the foregoing problems, there still exists a need to provide improved DMOS fabrication methods and process sequences.